Common-Mode Feedback Circuit

ABSTRACT

A differential amplifier circuit with common-mode feedback is disclosed. The amplifier may include a first stage comprising a first differential input configured to drive a first differential pair transistor in a first differential current path, a second differential input configured to drive a second differential pair transistor in a second differential current path, a first differential output, and a second differential output, a second stage comprising a first differential input, a second differential input, a first differential output, and a second differential output, a common-mode feedback circuit, a first conducting element in a first common-mode current path parallel to the first differential current path and comprising a first conducting terminal coupled to the first differential output of the first stage, and a second conducting element in a second common-mode current path parallel to the second differential current path and comprising a first conducting terminal coupled to the second differential output of the first stage.

RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. §119(e) of U.S.Provisional Application Ser. No. 61/423,862 filed Dec. 16, 2010.

TECHNICAL FIELD

The present invention relates generally to electrical circuits, and moreparticularly, to common-mode feedback in operational amplifiers.

BACKGROUND

Electrical circuits experience various types of noise, including but notlimited to thermal noise, shot noise, and 1/f noise. Many circuits, suchas operational amplifiers (amplifiers) are designed with a goal ofoptimizing the signal-to-noise ratio. One method to reduce noise in anamplifier may be to increase the gate size of field-effect transistors(FETs) used in the signal path. Commonly used FETs include NMOS and PMOStransistors. Increasing the gate size of a FET creates more gate areaover which the thermal noise associated with any one location in thegate may be averaged. Increasing the gate size of a FET may also reduce1/f noise. Examples of this technique may include using large FET sizesfor the differential pair or the matching current sources in the firststage of a multi-stage differential amplifier.

Amplifiers may also employ a common-mode feedback loop in order to keepthe common mode of a differential voltage signal at a proper operatinglevel. It may be desirable for this common-mode feedback loop to operateat high frequencies in a stable manner. However, increasing gate sizesof FETs in an amplifier to reduce noise will result in increasedgate-to-source capacitances for those FETs. Large capacitances in thecommon-mode feedback loop will limit the frequency at which the loopwill operate in a stable manner. Thus, when a traditional differentialamplifier employs a common-mode feedback loop, there may be a trade-offbetween reducing noise in the differential signal by using large FETs,and the frequency at which the common-mode feedback loop can operate ina stable manner.

Another problem for amplifiers employing an even number of invertingstages may be the potential for lock-up when feedback is utilized toclose the amplifier's signal loop. For example, an input signal with anoverly high or low common-mode may cause certain node voltages to swinghigh or low approaching the power supply or ground rails outside oftheir intended operating range. Certain transistors may be lockedoutside of their normal operating range, causing the amplifier as awhole to lock up in a stable but undesired state. The lock-up problemmay occur in multi-stage amplifiers where an even number of stages areinverting, including but not limited to FET-based topologies, bipolarjunction transistor (BJT)-based topologies, and combinations thereof.

SUMMARY

In accordance with some embodiments of the present disclosure, adifferential amplifier with common-mode feedback may include a firststage comprising a first differential input configured to drive a firstdifferential pair transistor in a first differential current path, asecond differential input configured to drive a second differential pairtransistor in a second differential current path, a first differentialoutput, and a second differential output, a second stage comprising afirst differential input, a second differential input, a firstdifferential output, and a second differential output, a common-modefeedback circuit, a first conducting element in a first common-modecurrent path parallel to the first differential current path andcomprising a first conducting terminal coupled to the first differentialoutput of the first stage, and a second conducting element in a secondcommon-mode current path parallel to the second differential currentpath and comprising a first conducting terminal coupled to the seconddifferential output of the first stage.

In accordance with some embodiments of the present disclosure, adifferential amplifier with common-mode feedback may include a firststage comprising a first differential input configured to drive a firstdifferential pair transistor in a first differential current path, asecond differential input configured to drive a second differential pairtransistor in a second differential current path, a first differentialoutput, and a second differential output, a second stage comprising afirst differential input, a second differential input, a firstdifferential output, and a second differential output, and a common-modefeedback circuit configured to drive a first conducting element and asecond conducting element, the first conducting element in a firstcommon-mode current path parallel to the first differential current pathand comprising a first conducting terminal coupled to the firstdifferential output of the first stage, the second conducting element ina second common-mode current path parallel to the second differentialcurrent path and comprising a first conducting terminal coupled to thesecond differential output of the first stage.

Technical advantages of one or more embodiments of the presentdisclosure may include reducing noise in an operational amplifier whilemaintaining sufficient common-mode feedback performance and preventinglock-up when the amplifier experiences an overly high or overly lowcommon-mode input signal.

It will be understood that the various embodiments of the presentdisclosure may include some, all, or none of the enumerated technicaladvantages. In addition, other technical advantages of the presentdisclosure may be readily apparent to one skilled in the art from thefigures, description and claims included herein.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and itsfeatures and advantages, reference is now made to the followingdescription, taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 illustrates a schematic diagram of an example fully differentialamplifier with common-mode feedback, in accordance with certainembodiments of the present disclosure;

FIG. 2 illustrates a schematic diagram of another example fullydifferential amplifier with common-mode feedback, in accordance withcertain embodiments of the present disclosure; and

FIG. 3 illustrates a schematic diagram of another example fullydifferential amplifier with common-mode feedback, in accordance withcertain embodiments of the present disclosure.

DETAILED DESCRIPTION

Some embodiments of the present disclosure provide a multi-stage fullydifferential amplifier with a common-mode feedback loop that may not belimited by large gate capacitances of FETs in the differential signalpath of the first stage. Some embodiments provide a multi-stage fullydifferential amplifier with a common mode current path that preventslock-up.

FIG. 1 illustrates a schematic diagram of a multi-stage fullydifferential amplifier 100, in accordance with certain embodiments ofthe present disclosure. The amplifier 100 may include a first stage 11,a second stage 12, a common-mode feedback circuit 30, a first conductingelement 151, and a second conducting element 152. Power may be suppliedto amplifier 100 through a high potential power supply and a lowpotential power supply. For the purposes of this disclosure, a highpotential power supply may be referred to as VDD, and a low potentialpower supply may be referred to as GND.

As shown in FIG. 1, the first stage 11 may have a first differentialinput, a second differential input, a first differential output, and asecond differential output. The first differential input of the firststage 11 may be coupled to the first differential input V⁺ _(in) of theamplifier 100, and the second differential input of the first stage 11may be coupled to the second differential input V⁻ _(in) of theamplifier 100. The first differential output of the first stage 11 maybe coupled to node 105, and the second differential output of the firststage 11 may be coupled to node 106.

The first stage 11 of the amplifier 100 may include a PMOS currentsource 171, PMOS differential pair transistors 141, 142, PMOS cascodetransistors 131, 132, NMOS cascode transistors 121, 122, and NMOScurrent sources 111, 112. The source of PMOS current source 171 may becoupled to VDD, and PMOS current source 171 may be driven at its gate bya bias voltage B5. The sources of the PMOS differential pair transistors141, 142 may be coupled together in a common source configuration andmay be further coupled to the drain of the PMOS current source 171. Thefirst PMOS differential pair transistor 141 may receive the firstdifferential input V⁺ _(in), and the second PMOS differential pairtransistor 142 may receive the second differential input V⁻ _(in). Therespective drains of the first and second differential pair transistors141, 142 may be coupled to the sources of PMOS cascode transistors 131,132. The PMOS cascode transistors 131, 132 may be driven at their gatesby a bias voltage B3. The respective drains of the PMOS cascodetransistors 131, 132 may be coupled to the drains of the NMOS cascodetransistors 121, 122, which may be driven at their gates by a biasvoltage B2. The respective sources of NMOS cascode transistors 121, 122may be coupled to the drains of NMOS current sources 111, 112. Thesources of NMOS current sources 111, 112 may be coupled to GND, and theNMOS current sources 111, 112 may be driven at their gates by theV_(ctrl) signal from the common-mode feedback circuit 30.

As shown in FIG. 1, the second stage 12 of the amplifier 100 may have afirst differential input, a second differential input, a firstdifferential output, and a second differential output. The firstdifferential input of the second stage 12 may be coupled to node 105,and the second differential input of the second stage 12 may be coupledto node 106. The first differential output of the second stage 12 may becoupled to the first differential output V⁺ _(out) of the amplifier 100,and the second differential output of the second stage 12 may be coupledto the second differential output V⁻ _(out) of the amplifier 100.

The first differential output of the first stage 11 may be coupled tothe first differential input of the second stage 12 at node 105, and thesecond differential output of the first stage 11 may be coupled to thesecond differential input of the second stage 12 at node 106. In somealternative embodiments, the signal paths between the respective outputsof the first stage and the inputs of the second stage may include one ormore other stages, one or more other conducting devices, or combinationsthereof. In such alternative embodiments the outputs of the first stageand the inputs of the second stage are still to be considered coupledtogether.

The second stage 12 in amplifier 100 may include PMOS current sources173, 174, PMOS cascode transistors 163, 164, compensation resistors 102,104, compensation capacitors 101, 103, NMOS cascode transistors 123,124, and NMOS transistors 113, 114. The sources of PMOS current sources173, 174 may be coupled to VDD, and the PMOS current sources 173, 174may be driven at their respective gates by a bias voltage B5. Therespective drains of PMOS current sources 173, 174 may be coupled to thesources of PMOS cascode transistors 163, 164, which may be driven attheir gates by a bias voltage B4. The drain of PMOS cascode transistor163 may be coupled to the first differential output V⁺ _(out), and thedrain of PMOS cascode transistor 164 may be coupled to the seconddifferential output V⁻ _(out). The respective drains of PMOS cascodetransistors 163, 164 may be further coupled to the drains of NMOScascode transistors 123, 124, which may be driven at their gates by abias voltage B2. The respective sources of NMOS cascode transistors 123,124 may be coupled to the drains of NMOS transistors 113, 114. Thesources of NMOS transistors 113, 114 may be coupled to GND. First NMOStransistor 113 may have a gate coupled to node 105 and may be driven bythe first differential input of the second stage 12. Second NMOStransistor 114 may have a gate coupled to node 106 and may be driven bythe second differential input of the second stage 12. For frequencycompensation, a resistor 102 and a capacitor 101 may be coupled inseries between the first differential input and the first differentialoutput of the second stage 12, and a resistor 104 and a capacitor 103may be coupled in series between the second differential input and thesecond differential output of the second stage 12.

As shown in FIG. 1, the common-mode feedback circuit 30 may monitor thecommon-mode voltage of V⁺ _(out) and V⁻ _(out). The common-mode sensecircuit 50 may sense the common-mode voltage of V⁺ _(out) and V⁻ _(out).The positive input to amplifier 40 may be coupled to a voltage referenceV_(ref), and the negative input to amplifier 40 may be coupled to theoutput of the common-mode sense circuit 50. Accordingly, the common-modevoltage of V⁺ _(out) and V⁻ _(out) may be measured by amplifier 40against the reference voltage V_(ref). The amplifier 40 may generate thecommon-mode feedback signal, V_(ctrl).

As shown in FIG. 1, the common-mode feedback loop may be formed bydriving the gates of the first and second NMOS current sources 111, 112with the common-mode feedback signal V_(ctrl). The V_(ctrl) signal maydrive the first and second NMOS current sources 111, 112 in a mannerwhich may keep the common-mode of the differential outputs of the firststage 11 within a desired range regardless of the common mode of the V⁺_(in) and V⁻ _(in) inputs. Accordingly, the differential inputs of thesecond stage 12 will be driven at a voltage within a desired operatingrange, and the second stage 12 may drive the differential output, V⁺_(out) and V⁻ _(out), within a desired output range.

In some alternative embodiments, the common-mode feedback loop may beformed by driving other devices in the first stage 11 or by injectingcurrent into or sinking current from other nodes within the first stage11. For example, in some alternative embodiments, the gates of NMOScurrent sources 111, 112 may be driven by a bias voltage while the gateof PMOS current source 171 may be driven by the common-mode feedbacksignal V_(ctrl).

As shown in FIG. 1, the first conducting element 151 may have a firstconducting terminal coupled to the first differential output of thefirst stage 11 at node 105. The second conducting element 152 may have afirst conducting terminal coupled to the second differential output ofthe first stage 11 at node 106. The first conducting element 151 and thesecond conducting element 152 may be comprised of instantiations ofcomponents independent from the instantiations of components forming thefirst stage 11 and the second stage 12.

The first conducting element 151 may have a second conducting terminalcoupled to a high potential power supply VDD. The first conductingelement 151 may comprise a PMOS transistor driven at its gate by a biasvoltage B6. The drain of the PMOS transistor may form the firstconducting terminal of the first conducting element 151, and the sourceof the PMOS transistor may form the second conducting terminal of thefirst conducting element 151. The second conducting element 152 maycomprise a PMOS transistor driven at its gate by a bias voltage B6. Thedrain of the PMOS transistor may form the first conducting terminal ofthe second conducting element 152, and the source of the PMOS transistormay form the second conducting terminal of the second conducting element152. In some alternative embodiments, the first and second conductingelements 151, 152 may comprise one or more devices including but notlimited to PMOS transistors, NMOS transistors, bipolar-junctiontransistors, JFETs, diodes, resistors, and combinations thereof. Someembodiments of the first and second conducting elements 151, 152 maycomprise self-biased devices, including but not limited to PMOStransistors, NMOS transistors, bipolar-junction transistors, JFETs. Someembodiments the first and second conducting elements 151, 152 maycomprise devices that require no biasing including but not limited toresistors and diodes.

The common-mode paths 153, 154 into the first-stage differential outputsmay prevent lock-up. When an overly high or overly low common-mode inputat V⁺ _(in) and V⁻ _(in) causes certain node voltages in the first stage11 to swing high or low outside of their intended operating range,certain transistors in the first stage 11 may be locked outside of theirnormal operating range. For example, in the embodiment illustrated inFIG. 1, when an overly high common-mode input at V⁺ _(in) and V⁻ _(in)is experienced, the differential pair transistors 141, 142 may not havethe necessary gate-to-source threshold voltage to operate. With thedifferential pair transistors 141, 142 turned off, the voltage potentialof the first and second differential outputs of the first stage 11 maydrop. If the outputs of the first stage were allowed to drop to avoltage insufficient to drive the second stage, the V⁺ _(out) and V⁻_(out) outputs of the amplifier 100 could rise and approach the voltageof the high potential power supply VDD, and in a configuration where V⁺_(out) and V⁻ _(out) are coupled through a feedback network to V⁺ _(in)and V⁻ _(in), the amplifier 100 could lock-up in a stable but undesiredstate. However, as shown in FIG. 1, the first conducting element 151 andthe second conducting element 152 may provide trickle currents to thefirst and second outputs of the first stage 11 outputs coupled to nodes105 and 106. The first conducting element 151 and the second conductingelement 152 may comprise instantiations of devices independent from theinstantiations of devices that form the first stage 11 and the secondstage 12. Accordingly, the common-mode current paths 153, 154 will notbe affected by transistors in the first stage that have turned off inresponse to an overly high or overly low common-mode input. Thecommon-mode current paths 153, 154 may keep the differential outputs ofthe first stage 11 at a sufficient voltage potential to drive the secondstage 12, preventing the possibility of lock-up.

In order to reduce current consumption, the trickle currents provided bythe common-mode current paths 153, 154 may be designed to besubstantially less than the bias currents of the first stage 11 andsecond stage 12. In some example embodiments, the ratio of the currentprovided by the PMOS current source to the trickle current may be ashigh as 100:1 or greater, while in some other example embodiments, theratio may be as low as 10:1 or less.

Some alternative embodiments of the differential amplifier 100 withcommon-mode feedback may include other multi-stage differentialamplifier topologies. Some alternative embodiments may include analternative first-stage topology, an alternative second-stage topology,an alternative common-mode feedback circuit topology, or combinationsthereof. Some alternative topologies may include the use other types oftransistors, including but not limited to bipolar-junction transistors,JFETs, and combinations thereof with NMOS and PMOS transistors.

The coupling of the second conducting terminals of the first and secondconducting elements 151, 152 may depend on the topology chosen for thefirst stage 11 of the amplifier 100. To ensure that the outputs of thefirst stage 11 are driven at a voltage potential sufficient to drivesecond stage 12, the common-mode current paths 153, 154 may operate inparallel to the differential current paths 143, 144 inside of the firststage 11. Accordingly, common-mode current paths 153, 154 may providecurrent to the differential outputs of the first stage 11 from VDD inparallel to the differential current paths 143, 144, which steer currentto the differential outputs of the first stage from the PMOS currentsource 171 coupled to VDD.

But, in some alternative embodiments, the common-mode current paths maysink current from the differential outputs in the first stage. Forexample, in some alternative embodiments, the first stage may include anNMOS differential pair steering differential current paths that sinkcurrent from the differential outputs of the first stage to a currentsource coupled to GND. Accordingly, in some alternative embodiments, toensure that the outputs of the first stage are driven at a voltagepotential capable to drive the second stage, the common-mode currentpaths may sink current from the differential outputs of the first stageto the low potential power supply GND.

FIG. 2 illustrates a schematic diagram of a multi-stage fullydifferential amplifier 200, in accordance with certain embodiments ofthe present disclosure. The amplifier 200 may include a first stage 21,a second stage 22, a common-mode feedback circuit 30, a first conductingelement 251, and a second conducting element 252. The first conductingelement 251 and the second conducting element 252 may be driven by thecommon-mode feedback circuit 30.

As shown in FIG. 2, the first stage 21 may have a first differentialinput, a second differential input, a first differential output, and asecond differential output. The first differential input of the firststage 21 may be coupled to the first differential input V⁺ _(in) of theamplifier 200, and the second differential input of the first stage 21may be coupled to the second differential input V⁻ _(in) of theamplifier 200. The first differential output of the first stage 21 maybe coupled to node 205, and the second differential output of the firststage 21 may be coupled to node 206.

The first stage 21 of the amplifier 200 may include a PMOS currentsource 171, PMOS differential pair transistors 141, 142, PMOS cascodetransistors 131, 132, NMOS cascode transistors 121, 122, and NMOScurrent sources 211, 212. The source of PMOS current source 171 may becoupled to VDD, and the PMOS current source 171 may be driven at itsgate by a bias voltage B5. The sources of the PMOS differential pairtransistors 141, 142 may be coupled together in a common sourceconfiguration and may be further coupled to the drain of the PMOScurrent source 171. The first PMOS differential pair transistor 141 mayreceive the first differential input V⁺ _(in) and the second PMOSdifferential pair transistor 142 may receive the second differentialinput V⁻ _(in). The respective drains of the first and seconddifferential pair transistors 141, 142 may be coupled to the sources ofPMOS cascode transistors 131, 132. The PMOS cascode transistors 131, 132may be driven at their gates by a bias voltage B3. The respective drainsof the PMOS cascode transistors 131, 132 may be coupled to the drains ofthe NMOS cascode transistors 121, 122, which may be driven at theirgates by a bias voltage B2. The respective sources of NMOS cascodetransistors 121, 122 may be coupled to the drains of NMOS currentsources 211, 212. The sources of NMOS current sources 211, 212 may becoupled to GND, and NMOS current sources 211, 212 may be driven at theirgates by a bias voltage B1.

As shown in FIG. 2, the second stage 22 of the amplifier 200 may have afirst differential input, a second differential input, a firstdifferential output, and a second differential output. The firstdifferential input of the second stage 22 may be coupled to node 205,and the second differential input of the second stage 22 may be coupledto node 206. The first differential output of the second stage 22 may becoupled to the first differential output V⁺ _(out) of the amplifier 200,and the second differential output of the second stage 22 may be coupledto the second differential output V⁻ _(out) of the amplifier 200.

The first differential output of the first stage 21 may be coupled tothe first differential input of the second stage 22 at node 205, and thesecond differential output of the first stage 21 may be coupled to thesecond differential input of the second stage 22 at node 206. In somealternative embodiments, the signal paths between the respective outputsof the first stage and the inputs of the second stage may include one ormore other stages, one or more other conducting devices, or combinationsthereof. In such alternative embodiments the outputs of the first stageand the inputs of the second stage are still to be considered coupledtogether.

The second stage 22 in amplifier 200 may include PMOS current sources173, 174, PMOS cascode transistors 163, 164, compensation resistors 102,104, compensation capacitors 101, 103, NMOS cascode transistors 123,124, and NMOS transistors 113, 114. The sources of PMOS current sources173, 174 may be coupled to VDD, and the PMOS current sources 173, 174may be driven at their respective gates by a bias voltage B5. Therespective drains of PMOS current sources 173, 174 may be coupled to thesources of PMOS cascode transistors 163, 164, which may be driven attheir gates by a bias voltage B4. The drain of PMOS cascode transistor163 may be coupled to the first differential output V⁺ _(out), and thedrain of PMOS cascode transistor 164 may be coupled to the seconddifferential output V⁻ _(out). The respective drains of PMOS cascodetransistors 163, 164 may be further coupled to the drains of NMOScascode transistors 123, 124, which may be driven at their gates by abias voltage B2. The respective sources of NMOS cascode transistors 123,124 may be coupled to the drains of NMOS transistors 113, 114, and thesources of NMOS transistors 113, 114 may be coupled to GND. First NMOStransistor 113 may have a gate coupled to node 205 and may be driven bythe first differential input of the second stage 22. Second NMOStransistor 114 may have a gate coupled to node 206 and may be driven bythe second differential input of the second stage 22. For compensation,a resistor 102 and a capacitor 101 may be coupled in series between thefirst differential input and the first differential output of the secondstage 22, and a resistor 104 and a capacitor 103 may be coupled inseries between the second differential input and the second differentialoutput of the second stage 22.

As shown in FIG. 2, the common-mode feedback circuit 30 may monitor thecommon-mode voltage of V⁺ _(out) and V⁻ _(out). The common-mode sensecircuit 50 may sense the common-mode voltage of V⁺ _(out) and V⁻ _(out).The positive input to amplifier 40 may be coupled to a voltage referenceV_(ref), and the negative input to amplifier 40 may be coupled to theoutput of the common-mode sense circuit 50. Accordingly, the common-modevoltage of V⁺ _(out) and V⁻ _(out) may be measured by amplifier 40against the reference voltage V_(ref). The amplifier 40 may generate thecommon-mode feedback signal, V_(ctrl).

As shown in FIG. 2, the common-mode feedback loop may be formed bydriving the first conducting element 251 and the second conductingelement 252 with the common-mode feedback signal V_(ctrl). The V_(ctrl)signal may drive the first and second conducting elements 251, 252 in amanner which may keep the common-mode of the differential outputs of thefirst stage 21 within a desired range regardless of the common mode ofthe V⁺ _(in) and V⁻ _(in) inputs. Accordingly, the differential inputsof the second stage 22 will be driven at a voltage within a desiredoperating range, and the second stage 22 may drive the differentialoutput, V⁺ _(out) and V⁻ _(out), within a desired output range.

The first conducting element 251 may have a first conducting terminalcoupled to the first differential output of the first stage 21 at node205. The second conducting element 252 may have a first conductingterminal coupled to the second differential output of the first stage 21at node 206. The first conducting element 251 and the second conductingelement 252 may be comprised of instantiations of components independentfrom the instantiations of components forming the first stage 21 and thesecond stage 22.

The first conducting element 251 may have a second conducting terminalcoupled to a high potential power supply VDD. The first conductingelement 251 may comprise a PMOS transistor. The drain of the PMOStransistor may form the first conducting terminal of the firstconducting element 251, and the source of the PMOS transistor may formthe second conducting terminal of the first conducting element 251. Thesecond conducting element 252 may have a second conducting terminalcoupled to a high potential power supply VDD. The second conductingelement 252 may comprise a PMOS transistor. The drain of the PMOStransistor may form the first conducting terminal of the secondconducting element 252, and the source of the PMOS transistor may formthe second conducting terminal of the second conducting element 252. Insome alternative embodiments, the first and second conducting elements251, 252 may comprise one or more devices, including but not limited toPMOS transistors, NMOS transistors, bipolar-junction transistors, JFETs,diodes, resistors, and combinations thereof.

As shown in FIG. 2, the first conducting element 251 may provide acommon-mode path 253 into the first differential output of the firststage 21, and the second conducting element 252 may provide acommon-mode path 254 into the second differential output of the firststage 21. Common-mode paths 253, 254 may be separate from thedifferential mode paths 243, 244 in the first stage 21. Accordingly, thecommon-mode feedback loop does not overlap with the differential modepaths 243, 244 in the first stage 21. Thus, the common-mode feedbackloop may operate in a manner that may be not substantially limited bythe characteristics of the first stage 21. In particular, the frequencyat which the common-mode feedback loop may operate in a stable mannermay be unaffected by the sizes of the gate-to-source capacitances ofcertain transistors in the first stage 21. The PMOS differential pairtransistors 141, 142 and the NMOS current sources 211, 212 may havelarge gate sizes to minimize thermal noise and 1/f noise withoutimpacting the frequency at which the common-mode feedback loop canoperate in a stable manner.

Furthermore, the common-mode paths 253, 254 into the first-stagedifferential outputs may prevent lock-up. When an overly high or overlylow common-mode input at V⁺ _(in) and V⁻ _(in) causes certain nodevoltages in the first stage 21 to swing high or low outside of theirintended operating range, certain transistors in the first stage 21 maybe locked outside of their normal operating range. For example, when anoverly high common-mode input at V⁺ _(in) and V⁻ _(in) is experienced,the PMOS differential pair transistors 141, 142 may not have thenecessary gate-to-source threshold voltage to operate. With thedifferential pair transistors 141, 142 turned off, the voltage potentialof the first and second differential outputs of the first stage 21 maydrop. If the outputs of the first stage were allowed to drop to avoltage insufficient to drive the second stage, the V⁺ _(out) and V⁻_(out) outputs of the amplifier 200 could rise and approach the voltageof the high potential power supply VDD, and in a configuration where V⁺_(out) and V⁻ _(out) are coupled through a feedback network to V⁺ _(in)and V⁻ _(in), the amplifier 200 could lock-up in a stable but undesiredstate. However, the first conducting element 251 and the secondconducting element 252 may provide common-mode current paths 253, 254into the first-stage outputs that may be independent from transistors inthe first stage 21 that may be locked out of their normal operatingrange. Accordingly, the common-mode feedback loop will not be broken bytransistors in the first stage that have turned off in response to anoverly high or overly low common-mode input. Thus lock-up due to anoverly high or overly low common-mode input into V⁺ _(in) and V⁻ _(in)may be prevented.

Some alternative embodiments of the differential amplifier 200 withcommon-mode feedback may include other multi-stage differentialamplifier topologies. Some alternative embodiments may include analternative first-stage topology, an alternative second-stage topology,an alternative common-mode feedback circuit topology, or combinationsthereof. Some alternative topologies may include the use other types oftransistors, including but not limited to bipolar-junction transistors,JFETs, and combinations thereof with NMOS and PMOS transistors.

FIG. 3 illustrates a schematic diagram of a multi-stage fullydifferential amplifier 300, in accordance with certain embodiments ofthe present disclosure. The amplifier 300 may include a first stage 31,a second stage 32, a common-mode feedback circuit 30, a first conductingelement 351, and a second conducting element 352. The first conductingelement 351 and the second conducting element 352 may be driven by thecommon-mode feedback circuit 30.

As shown in FIG. 3, the first stage 31 may have a first differentialinput, a second differential input, a first differential output, and asecond differential output. The first differential input of the firststage 31 may be coupled to the first differential input V⁺ _(in) of theamplifier 300, and the second differential input of the first stage 31may be coupled to the second differential input V⁻ _(in) of theamplifier 300. The first differential output of the first stage 31 maybe coupled to node 305, and the second differential output of the firststage 31 may be coupled to node 306.

The first stage 31 of the amplifier 300 may include an NMOS currentsource 371, NMOS differential pair transistors 341, 342, NMOS cascodetransistors 331, 332, PMOS cascode transistors 321, 322, and PMOScurrent sources 311, 312. The source of NMOS current source 371 may becoupled to GND, and the NMOS current source 371 may be driven at itsgate by a bias voltage B15. The sources of the NMOS differential pairtransistors 341, 342 may be coupled together in a common-sourceconfiguration and may be further coupled to the drain of the NMOScurrent source 371. The first NMOS differential pair transistor 341 mayreceive the first differential input V⁺ _(in) and the second NMOSdifferential pair transistor 342 may receive the second differentialinput V⁻ _(in). The respective drains of the first and seconddifferential pair transistors 341, 342 may be coupled to the sources ofNMOS cascode transistors 331, 332. The NMOS cascode transistors 331, 332may be driven at their gates by a bias voltage B13. The respectivedrains of NMOS cascode transistors 331, 332, may be coupled to thedrains of PMOS cascode transistors 321, 322, which may be driven attheir gates by a bias voltage B12. The respective sources of PMOScascode transistors 321, 322 may be coupled to the drains of PMOScurrent sources 311, 312. The sources of PMOS current sources 311, 312may be coupled to VDD, and PMOS current sources 311, 312 may be drivenat their gates by a bias voltage B11.

As shown in FIG. 3, the second stage 32 of the amplifier 300 may have afirst differential input, a second differential input, a firstdifferential output, and a second differential output. The firstdifferential input of the second stage 32 may be coupled to node 305,and the second differential input of the second stage 32 may be coupledto node 306. The first differential output of the second stage 32 may becoupled to the first differential output V⁺ _(out) of the amplifier 300,and the second differential output of the second stage 32 may be coupledto the second differential output V⁻ _(out) of the amplifier 300.

The first differential output of the first stage 31 may be coupled tothe first differential input of the second stage 32 at node 305, and thesecond differential output of the first stage 31 may be coupled to thesecond differential input of the second stage 32 at node 306. In somealternative embodiments, the signal paths between the respective outputsof the first stage and the inputs of the second stage may include one ormore other stages, one or more other conducting devices, or combinationsthereof. In such alternative embodiments the outputs of the first stageand the inputs of the second stage are still to be considered coupledtogether.

The second stage 32 in amplifier 300 may include NMOS current sources373, 374, NMOS cascode transistors 363, 364, compensation resistors 302,304, compensation capacitors 301, 303, PMOS cascode transistors 323,324, and PMOS transistors 313, 314. The sources of NMOS current sources373, 374 may be coupled to GND, and the NMOS current sources 373, 374may be driven at their respective gates by a bias voltage B15. Therespective drains of NMOS current sources 373, 374 may be coupled to thesources of NMOS cascode transistors 363, 364, which may be driven attheir gates by a bias voltage B14. The drain of NMOS cascode transistor363 may be coupled to the first differential output V⁺ _(out), and thedrain of NMOS cascode transistor 364 may be coupled to the seconddifferential output V⁻ _(out). The respective drains of NMOS cascodetransistors 363, 364 may be further coupled to the drains of PMOScascode transistors 323, 324, which may be driven at their gates by abias voltage B12. The respective sources of PMOS cascode devices 323,324 may be coupled to the drains of PMOS transistors 313, 314, and thesources of PMOS transistors 313, 314 may be coupled to VDD. First PMOStransistor 313 may have a gate coupled to node 305 and may be driven bythe first differential input of the second stage 32. Second PMOStransistor 314 may have a gate coupled to node 306 and may be driven bythe second differential input of the second stage 32. For compensation,a resistor 302 and a capacitor 301 may be coupled in series between thefirst differential input and the first differential output V⁺ _(out) ofthe second stage 32, and a resistor 304 and a capacitor 303 may becoupled in series between the second differential input and the seconddifferential output V⁻ _(out) of the second stage 32.

As shown in FIG. 3, the common-mode feedback circuit 30 may monitor thecommon-mode voltage of V⁺ _(out) and V⁻ _(out). The common-mode sensecircuit 50 may sense the common-mode voltage of V⁺ _(out) and V⁻ _(out).The positive input to amplifier 40 may be coupled to a voltage referenceV_(ref), and the negative input to amplifier 40 may be coupled to theoutput of the common-mode sense circuit 50. Accordingly, the common-modevoltage of V⁺ _(out) and V⁻ _(out) may be measured by amplifier 40against the reference voltage V_(ref). The amplifier 40 may generate thecommon-mode feedback signal, V_(ctrl).

As shown in FIG. 3, the common-mode feedback loop may be formed bydriving the gates of the first conducting element 351 and the secondconducting element 352 with the common-mode feedback signal V_(ctrl).The V_(ctrl) signal may drive the first and second conducting elements351, 352 in a manner which may keep the common-mode of the differentialoutputs of the first stage 31 within a desired range regardless of thecommon mode of the V⁺ _(in) and V⁻ _(in) inputs. Accordingly, thedifferential inputs of the second stage 32 will be driven at a voltagewithin a desired operating range, and the second stage 32 may drive thedifferential output, V⁺ _(out) and V⁻ _(out), within a desired outputrange.

The first conducting element 351 may have a first conducting terminalcoupled to the first differential output of the first stage 31 at node305. The second conducting element 352 may have a first conductingterminal coupled to the second differential output of the first stage 31at node 306. The first conducting element 351 and the second conductingelement 352 may be comprised of instantiations of components independentfrom the instantiations of components forming the first stage 31 and thesecond stage 32.

The first conducting element 351 may have a second conducting terminalcoupled to a low potential power supply GND. The first conductingelement 351 may comprise an NMOS transistor. The drain of the NMOStransistor may form the first conducting terminal of the firstconducting element 351, and the source of the NMOS transistor may formthe second conducting terminal of the first conducting element 351. Thesecond conducting element 352 may have a second conducting terminalcoupled to a low potential power supply GND. The second conductingelement 352 may comprise an NMOS transistor. The drain of the NMOStransistor may form the first conducting terminal of the secondconducting element 352, and the source of the NMOS transistor may formthe second conducting terminal of the second conducting element 352. Insome alternative embodiments, the first and second conducting elements351, 352 may comprise one or more devices, including but not limited toPMOS transistors, NMOS transistors, bipolar-junction transistors, JFETs,diodes, resistors, and combinations thereof.

As shown in FIG. 3, the first conducting element 351 may provide acommon-mode path 353 into the first differential output of the firststage 31, and the second conducting element 352 may provide acommon-mode path 354 into the second differential output of the firststage 31. Common-mode paths 353, 354 may be separate from thedifferential mode paths 343, 344 in the first stage 31. The common-modefeedback loop does not overlap with the differential mode paths 343, 344in the first stage 31. Thus, the common-mode feedback loop may operatein a manner that may be not substantially limited by the characteristicsof the first stage 31. In particular, the frequency at which thecommon-mode feedback loop may operate in a stable manner may beunaffected by the sizes of the gate-to-source capacitances of certaintransistors in the first stage 31. Accordingly, the NMOS differentialpair transistors 341, 342 and the PMOS current sources 311, 312 may havelarge gate sizes to minimize thermal noise and 1/f noise withoutimpacting the frequency at which the common-mode feedback loop canoperate in a stable manner.

Furthermore, the common-mode paths 353, 354 into the first-stagedifferential outputs may prevent lock-up. When an overly high or overlylow common-mode input at V⁺ _(in) and V⁻ _(in) causes certain nodevoltages in the first stage 31 to swing high or low outside of theirintended operating range, certain transistors in the first stage 31 maybe locked outside of their normal operating range. For example, when anoverly low common-mode input at V⁺ _(in) and V⁻ _(in) is experienced,the NMOS differential pair transistors 341, 342 may not have thenecessary gate-to-source threshold voltage to operate. With thedifferential pair transistors 341, 342 turned off, the voltage potentialof the first and second differential outputs of the first stage 31 mayrise. If the outputs of the first stage were allowed to rise to avoltage too high to drive the second stage 32, the V⁺ _(out) and V⁻_(out) outputs of the amplifier 300 could drop and approach the voltageof the low potential power supply GND, and in a configuration where V⁺_(out) and V⁻ _(out) are coupled through a feedback network to V⁺ _(in)and V⁻ _(in), the amplifier 300 could lock-up in a stable but undesiredstate. However, the first conducting element 351 and the secondconducting element 352 may provide common-mode current paths 353, 354into the first-stage outputs that may be independent from transistors inthe first stage 31 that may be locked out of their normal operatingrange. Accordingly, the common-mode feedback loop will not be broken bytransistors in the first stage that have turned off in response to anoverly high or overly low common-mode input. Thus lock-up due to anoverly high or overly low common-mode input into V⁺ _(in) and V⁻ _(in)may be prevented.

Some alternative embodiments of the differential amplifier 300 withcommon-mode feedback as shown in FIG. 3 may include other multi-stagedifferential amplifier topologies. Some alternative embodiments mayinclude an alternative first-stage topology, an alternative second-stagetopology, an alternative common-mode feedback circuit topology, orcombinations thereof. Some alternative topologies may include the useother types of transistors, including but not limited tobipolar-junction transistors, JFETs, and combinations thereof with NMOSand PMOS transistors.

The coupling of the second conducting terminals of the conductingelements in various embodiments may depend on the topology chosen forthe first stage of an amplifier. For example, as shown by the embodimentillustrated in FIG. 2, to ensure that the outputs of the first stage 21are driven at a voltage potential sufficient to drive the second stage22, the common-mode current paths 253, 254 may operate in parallel tothe differential current paths 243, 244 inside of the first stage 21.Accordingly, common-mode current paths 253, 254 may provide current fromVDD to the differential outputs of the first stage 21 in parallel to thedifferential current paths 243, 244, which steer current to thedifferential outputs of the first stage 21 from the PMOS current source171 coupled to VDD.

But in some embodiments, the common-mode current paths may sink currentfrom the differential outputs in the first stage. For example, as shownby the embodiment illustrated in FIG. 3, to ensure that the outputs ofthe first stage 31 are driven at a voltage potential sufficient to drivethe second stage 32, the common-mode current paths 353, 354 may operatein parallel to the differential current paths 343, 344 inside of thefirst stage 31. Accordingly, common-mode current paths 353, 354 may sinkcurrent from the differential outputs of the first stage 31 to GND inparallel to the differential current paths 343, 344, which may sinkcurrent from the differential outputs of the first stage 31 to the NMOScurrent source 371 coupled to GND.

1. A differential amplifier with common-mode feedback comprising: afirst stage comprising a first differential input configured to drive afirst differential pair transistor in a first differential current path,a second differential input configured to drive a second differentialpair transistor in a second differential current path, a firstdifferential output, and a second differential output; a second stagecomprising a first differential input, a second differential input, afirst differential output, and a second differential output; acommon-mode feedback circuit; a first conducting element in a firstcommon-mode current path parallel to the first differential current pathand comprising a first conducting terminal coupled to the firstdifferential output of the first stage; and a second conducting elementin a second common-mode current path parallel to the second differentialcurrent path and comprising a first conducting terminal coupled to thesecond differential output of the first stage.
 2. The amplifier of claim1 wherein the common-mode feedback circuit is configured to drive acurrent source in the first stage.
 3. The amplifier of claim 2, wherein:the first conducting element comprises a second conducting terminalcoupled to a high potential power supply; and the second conductingelement comprises a second conducting terminal coupled to a highpotential power supply.
 4. The amplifier of claim 3, wherein the firstconducting element comprises a PMOS transistor and the second conductingelement comprises a PMOS transistor.
 5. The amplifier of claim 3,wherein the second stage comprises: a first NMOS transistor comprising agate configured to be driven by the first input of the second stage; anda second NMOS transistor comprising a gate configured to be driven bythe second input of the second stage.
 6. The amplifier of claim 2,wherein: the first conducting element comprises a second conductingterminal coupled to a low potential power supply; and the secondconducting element comprises a second conducting terminal coupled to alow potential power supply.
 7. The amplifier of claim 6, wherein thefirst conducting element comprises an NMOS transistor and the secondconducting element comprises an NMOS transistor.
 8. The amplifier ofclaim 6, wherein the second stage comprises: a first PMOS transistorcomprising a gate configured to be driven by the first input of thesecond stage; and a second PMOS transistor comprising a gate configuredto be driven by the second input of the second stage.
 9. A differentialamplifier circuit with common-mode feedback comprising: a first stagecomprising a first differential input configured to drive a firstdifferential pair transistor in a first differential current path, asecond differential input configured to drive a second differential pairtransistor in a second differential current path, a first differentialoutput, and a second differential output; a second stage comprising afirst differential input, a second differential input, a firstdifferential output, and a second differential output; and a common-modefeedback circuit configured to drive a first conducting element and asecond conducting element, the first conducting element in a firstcommon-mode current path parallel to the first differential current pathand comprising a first conducting terminal coupled to the firstdifferential output of the first stage, the second conducting element ina second common-mode current path parallel to the second differentialcurrent path and comprising a first conducting terminal coupled to thesecond differential output of the first stage.
 10. The amplifier ofclaim 9, wherein: the first conducting element comprises a secondconducting terminal coupled to a high potential power supply; and thesecond conducting element comprises a second conducting terminal coupledto a high potential power supply.
 11. The amplifier of claim 10, whereinthe first conducting element comprises a PMOS transistor and the secondconducting element comprises a PMOS transistor.
 12. The amplifier ofclaim 10, wherein the second stage comprises: a first NMOS transistorcomprising a gate configured to be driven by the first input of thesecond stage; and a second NMOS transistor comprising a gate configuredto be driven by the second input of the second stage.
 13. The amplifierof claim 9, wherein: the first conducting element comprises a secondconducting terminal coupled to a low potential power supply; and thesecond conducting element comprises a second conducting terminal coupledto a low potential power supply.
 14. The amplifier of claim 13, whereinthe first conducting element comprises a first NMOS transistor and thesecond conducting element comprises a first NMOS transistor.
 15. Theamplifier of claim 13, wherein the second stage comprises: a first PMOStransistor comprising a gate configured to be driven by the first inputof the second stage; and a second PMOS transistor comprising a gateconfigured to be driven by the second input of the second stage.
 16. Amethod for providing common-mode feedback in a multi-stage amplifier,comprising: generating a common-mode feedback signal based on areference voltage and a common-mode value of a first differential outputand a second differential output of an amplifier; and driving a firstconducting element and a second conducting element with the common-modefeedback signal, the first conducting element in a first common-modecurrent path parallel to a first differential current path in a firststage and comprising a first conducting terminal coupled to a firstdifferential output of the first stage, the second conducting element ina second common-mode current path parallel to a second differentialcurrent path in the first stage and comprising a first conductingterminal coupled to a second differential output of the first stage. 17.The method of claim 16, wherein: the first conducting element comprisesa second conducting terminal coupled to a high potential power supply;and the second conducting element comprises a second conducting terminalcoupled to a high potential power supply.
 18. The method of claim 17,wherein the first conducting element comprises a PMOS transistor and thesecond conducting element comprises a PMOS transistor.
 19. The method ofclaim 16, wherein: the first conducting element comprises a secondconducting terminal coupled to a low potential power supply; and thesecond conducting element comprises a second conducting terminal coupledto a low potential power supply.
 20. The method of claim 19, wherein thefirst conducting element comprises a first NMOS transistor and thesecond conducting element comprises a first NMOS transistor.